The present invention relates to a device and method for use in electrically testing a chip.
With each new generation of integrated circuit technology, the number and the density of circuits increase on an integrated circuit. An integrated circuit is also referred to herein as a “chip” or a “die”. Not surprisingly, the number and the density of external interconnects to a chip tends to increase with the circuit density, to support increased data bandwidth, and in large part to provide sufficiently low impedance connections to supply power to internal locations of the chip. To help address the requirements for testing chips of increased complexity, built-in-self-test techniques have been developed which reduce the memory and speed requirements of automatic test equipment. However, the increased complexity has caused test time durations to increase substantially. Thus, methods to enable a lower cost test environment have been shifting gradually away from reliance on automatic test equipment and towards reduced pin test equipment which interfaces to the chip through a subset of the chip's external pins.
One chip packaging technology, which supports tightly pitched external interconnects, is known as “controlled collapse chip connection” (i.e., “C4”). The C4 process refers to the manner in which parallel disposed solder bumps formed on an external array of bond pads of the chip, are simultaneously joined to corresponding solder-wettable contact pads of the package element by “reflowing” (i.e., by melting and re-solidification of) the solder bumps to join the bumps to the contact pads of the package element.
While chip packaging systems have kept pace with the increasing density of external interconnects, it has become increasingly difficult to electrically test a bare (unpackaged) chip through its external interconnects. Wafer-level testing has provided a way of testing the functionality of chips before they are even severed from the wafer. Typically, a wafer-level tester has a stepper which steps to one chip location of the wafer, establishes conductive contact to external interconnects of that chip location, and conducts electrical testing at that chip location. Then, the stepper steps to another chip location of the wafer, establishes conductive contact to the other chip location, conducts testing at that chip location, and then repeats the same steps again for another chip location of the wafer.
Alignment in four (4) dimensions is automatically performed for each new wafer. The stepper can then step from one chip location to another automatically and conserve time by eliminating the time required to align the tester to individual chip locations in turn. However, when the test performed on a chip at each chip location is very time-consuming, an economic trade-off is made between the cost of the test and the extent of test coverage achieved for each chip location, the test coverage being a function of the time allotted to the test. Often, for the complex devices considered here, such systems are unable to test more than one chip location of the wafer at the same time due to power delivery and power dissipation issues. One major cost factor comes about because expensive equipment is required to align the external interconnects of a chip of the wafer to a matching wafer probe for testing. Another major cost factor is the test equipment which generally is in the class of equipment referred to as Automatic Test Equipment (ATE). Such equipment has multiple capabilities which result in the equipment being costly, particularly when used to test only one chip location of the wafer at a time.
On the other hand, for chips which are relatively less complex (e.g., chips which are usually smaller, have fewer input/output (I/O) connections and operate at lower power), multiple chip locations can be tested simultaneously in parallel to reduce the cost of testing each chip by a factor equal to the number of chip locations tested in parallel. Except for such less complex chips, testing must either be performed one chip location at a time using an expensive wafer prober and test equipment and/or testing must be performed on individual chips after the wafer has been severed into individual chips.
Heretofore, the time and expense required to align an individual chip of relatively high complexity to a test probe has been costly. Costly precision equipment, similar to that used on wafer probers, has been used to achieve correct alignment to establish conductive contact between the external interconnects of the chip and a probe interface. For relatively complex chips, one alternative has been to mount individual chips to temporary packages, test the chips as mounted to the temporary packages, i.e., via functional and/or burn-in tests, and then remove the temporary packages after the tests. The chips which show good test results are then mounted to final packages. Clearly, it would be desirable to eliminate the time and expense required to mount and remove temporary packages to test individual chips of relative complexity.
For these reasons, it would be desirable to provide a new way of testing individual “bare” chips, i.e., unpackaged chips, after wafers have been severed into individual chips, using equipment that is capable of accurately aligning the external interconnects of the bare chip to a probe interface without requiring costly precision alignment methods.
U.S. Pat. No. 6,002,266 to Briggs et al. (“the Briggs Patent”) describes a test socket for a chip which has sloped sidewalls. When placed in the socket, the edges of the chip rest against the sloped sidewalls. At best, the sloped sidewalls of the socket imprecisely align the chip within the socket because the chip remains free to move up and down along the sloped sidewalls. The socket described in the Briggs Patent falls short of locating a chip in a sufficiently precise manner to align fine pitch interconnects (e.g., C4 interconnects) of a chip to a mating array of probe contacts.
Recent advances in C4 process technology provide more tightly controlled tolerances, including tolerances specifying the placement of the bond pads on the chip relative to the edge of the chip. For example, the positional tolerance of bond pads of the chip has now been reduced to as low as 1 mil (i.e., 0.001 inch). With more tightly controlled tolerances, it would be desirable to provide a way of aligning or locating a chip within a retaining member of an electrical testing apparatus which does not require costly equipment or a large amount of time to perform.